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NLAS4051 Analog Multiplexer/ Demultiplexer
TTL Compatible, Single-Pole, 8-Position Plus Common Off
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The NLAS4051 is an improved version of the MC14051 and MC74HC4051 fabricated in sub-micron Silicon Gate CMOS technology for lower RDS(on) resistance and improved linearity with low current. This device may be operated either with a single supply or dual supply up to 3.0 V to pass a 6.0 VPP signal without coupling capacitors. When operating in single supply mode, it is only necessary to tie VEE, pin 7 to ground. For dual supply operation, VEE is tied to a negative voltage, not to exceed maximum ratings.
Features
MARKING DIAGRAMS
16 SOIC-16 D SUFFIX CASE 751B 1 NLAS4051G AWLYWW
1
16 TSSOP-16 DT SUFFIX CASE 948F 1 NLAS 4051 ALYWG G
* Improved RDS(on) Specifications * Pin for Pin Replacement for MAX4051 and MAX4051A *
One Half the Resistance Operating at 5.0 V Single or Dual Supply Operation Single 2.5-5.0 V Operation, or Dual 3.0 V Operation With VCC of 3.0 to 3.3 V, Device Can Interface with 1.8 V Logic, No Translators Needed Address and Inhibit Logic are Over-Voltage Tolerant and May Be Driven Up +6.0 V Regardless of VCC Improved Linearity Over Standard HC4051 Devices
1
16 QSOP-16 QS SUFFIX CASE 492 1 A WL, L Y WW, W G or G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package S4051 ALYW
1
* * Popular SOIC, and Space Saving TSSOP, and QSOP 16 Pin *
Packages Pb-Free Packages are Available*
VCC 16
NO2 15
NO4 14
NO0 13
NO6 ADDC ADDB ADDA 12 11 10 9
ORDERING INFORMATION
Device NLAS4051DR2 NLAS4051DR2G NLAS4051DTR2 Package SOIC-16 SOIC-16 (Pb-Free) Shipping 2500/Tape & Reel 2500/Tape & Reel
TSSOP-16 2500/Tape & Reel
1 NO1
2
3
4 NO7
5 NO5
6
7
8 GND
NO3 COM
Inhibit VEE
NLAS4051DTR2G TSSOP-16 2500/Tape & Reel (Pb-Free) NLAS4051QSR QSOP-16 2500/Tape & Reel
Figure 1. Pin Connection (Top View)
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
1
May, 2006 - Rev. 3
Publication Order Number: NLAS4051/D
NLAS4051
TRUTH TABLE
Address Inhibit 1 0 0 0 0 0 0 0 0 C X don't care 0 0 0 0 1 1 1 1 B X don't care 0 0 1 1 0 0 1 1 A X don't care 0 1 0 1 0 1 0 1 ON SWITCHES* NO2 All switches open COM-NO0 COM-NO1 COM-NO2 COM-NO3 COM-NO4 COM-NO5 COM-NO6 COM-NO7 ADDC ADDB ADDA LOGIC COM NO3 NO4 NO5 NO6 NO7 Inhibit NO0 NO1
*NO and COM pins are identical and interchangeable. Either may be considered an input or output; signals pass equally well in either direction.
Figure 2. Logic Diagram
IIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIII I IIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIII I IIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS
Parameter Symbol VEE Value Unit V V V V Negative DC Supply Voltage (Referenced to GND) -7.0 to )0.5 -0.5 to )7.0 -0.5 to )7.0 Positive DC Supply Voltage (Note 1) Analog Input Voltage Digital Input Voltage (Referenced to GND) (Referenced to VEE) VCC VIS VEE -0.5 to VCC )0.5 -0.5 to 7.0 $50 (Referenced to GND) VIN I DC Current, Into or Out of Any Pin Storage Temperature Range mA _C _C _C -65 to )150 260 TSTG TL TJ Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature under Bias Thermal Resistance )150 143 164 164 500 450 450 SOIC TSSOP QSOP SOIC TSSOP QSOP qJA C/W Power Dissipation in Still Air, PD mW Moisture Sensitivity MSL FR Level 1 Flammability Rating Oxygen Index: 30% - 35% UL 94 V-0 @ 0.125 in u2000 u200 u1000 $300 ESD Withstand Voltage Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) VESD V Latchup Performance Above VCC and Below GND at 125C (Note 5) ILATCHUP mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The absolute value of VCC $|VEE| 7.0. 2. Tested to EIA/JESD22-A114-A. 3. Tested to EIA/JESD22-A115-A. 4. Tested to JESD22-C101-A. 5. Tested to EIA/JESD78.
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NLAS4051
RECOMMENDED OPERATING CONDITIONS
I IIIII I IIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII I I IIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII I I IIIIIII IIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIII IIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII II III IIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII
Parameter Symbol VEE Min Max Unit V V V V Negative DC Supply Voltage Positive DC Supply Voltage Analog Input Voltage Digital Input Voltage (Referenced to GND) -5.5III GND 2.5 2.5 5.5 6.6 (Referenced to GND) (Referenced to VEE) VCC VIS VEE 0 VCC 5.5 (Note 6) (Referenced to GND) VIN TA Operating Temperature Range, All Package Types -55 0 0 125 100 20 _C Input Rise/Fall Time (Channel Select or Enable Inputs) VCC = 3.0 V $ 0.3 V VCC = 5.0 V $ 0.5 V tr, tf ns/V 6. Unused digital inputs may not be left open. All digital inputs must be tied to a high-logic voltage level or a low-logic input voltage level.
DC CHARACTERISTICS - Digital Section (Voltages Referenced to GND)
VCC V 2.5 3.0 4.5 5.5 2.5 3.0 4.5 5.5 0 V to 6.0 V 6.0 Guaranteed Limit -55 to 25C 1.75 2.1 3.15 3.85 .45 0.9 1.35 1.65 $0.1 4.0 v85C 1.75 2.1 3.15 3.85 .45 0.9 1.35 1.65 $1.0 40 v125C 1.75 2.1 3.15 3.85 .45 0.9 1.35 1.65 $1.0 80 Unit V
Parameter Minimum High-Level Input Voltage, Address and Inhibit Inputs
Condition
Symbol VIH
Maximum Low-Level Input Voltage, Address and Inhibit Inputs
VIL
V
Maximum Input Leakage Current, Address or Inhibit Inputs Maximum Quiescent Supply Current (per Package)
VIN = 6.0 or GND Address, Inhibit and VIS = VCC or GND
IIN ICC
mA mA
DC ELECTRICAL CHARACTERISTICS - Analog Section
I I IIIIIIIIIIIIII IIIIIIIII I II II IIIIIIIII IIIIIIIIIIIIII IIIIIIIII I II II IIIIIIIII II I I I II II I IIIIIIIIIIIIII IIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIII II I IIIIIIIIIIIIII IIIIIIIIIIIIIIIII I II II IIIIIIIII II I I I I I IIIIIIIIIIIIII IIIIIIIIIIIIIIIII IIIIIIIIIII I I II I I IIIIIIIIIIIIII IIIIIIIIIIIIIIIII I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I
Symbol Parameter Test Conditions VCC V 3.0 4.5 3.0 3.0 4.5 3.0 VEE V Guaranteed Limit v85_C 108 46 33 20 18 15 4 2 -55 to 25C 86 37 26 15 13 10 4 2 v125_C 120 55 37 20 18 15 5 3 Unit W Maximum "ON" Resistance (Note 7) VIN = VIL or VIH VIS = (VEE to VCC) |IS| = 10 mA (Figures 4 thru 9) RON 0 0 -3.0 0 0 -3.0 3.0 Maximum Difference in "ON" Resistance Between Any Two Channels in the Same Package VIN = VIL or VIH, VIS= 2.0 V VIS = 1/2 (VCC - VEE), VIS= 3.0 V |IS| = 10 mA, VIS= 2.0 V DRON W ON Resistance Flatness Maximum Off-Channel Leakage Current |IS| = 10 mA VCOM = 1, 2, 3.5 V VCOM = 2, 0, 2 V Rflat(ON) INC(OFF) INO(OFF) 4.5 3.0 W Switch Off VIN = VIL or VIH VIO = VCC -1.0 V or VEE +1.0 V (Figure 17) Switch On VIO = VCC -1.0 V or VEE +1.0 V (Figure 17) 6.0 3.0 0 -3.0 0.1 0.1 5.0 5.0 100 100 nA Maximum On-Channel Leakage Current, Channel- to-Channel ICOM(ON) 6.0 3.0 0 -3.0 0.1 0.1 5.0 5.0 100 100 nA 7. At supply voltage (VCC) approaching 2.5 V the analog switch on-resistance becomes extremely non-linear. Therefore, for low voltage operation it is recommended that these devices only be used to control digital signals.
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NLAS4051
AC CHARACTERISTICS (Input tr = tf = 3 ns)
IIIII I I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII II I I I IIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I
Guaranteed Limit Parameter Test Conditions Symbol tBBM VCC V 3.0 4.5 3.0 VEE V -55 to 25_C Min 1.0 1.0 1.0 Typ* 6.5 5.0 3.5 v85_C - - - v125_C - - - Unit ns Minimum Break-Before- Make Time VIN = VIL or VIH VIS = VCC RL = 300 W, CL = 35 pF (Figure 19) 0.0 0.0 -3.0 *Typical Characteristics are at 25_C.
AC CHARACTERISTICS (CL = 35 pF, Input tr = tf = 3 ns)
Guaranteed Limit VCC V 2.5 3.0 4.5 3.0 2.5 3.0 4.5 3.0 2.5 3.0 4.5 3.0 VEE V 0 0 0 -3.0 0 0 0 -3.0 0 0 0 -3.0 -55 to 25C Min Typ 22 20 16 16 22 18 16 16 22 18 16 16 Max 40 28 23 23 40 28 23 23 40 28 23 23 v85C Min Max 45 30 25 25 45 30 25 25 45 30 25 25 v125C Min Max 50 35 30 28 50 35 30 28 50 35 30 28 Unit ns
Parameter Transition Time (Address Selection Time) (Figure 18) Turn-on Time (Figures 14, 15, 20, and 21) Inhibit to NO or NC Turn-off Time (Figures 14, 15, 20, and 21) Inhibit to NO or NC
Symbol tTRANS
tON
ns
tOFF
ns
Typical @ 25C, VCC = 5.0 V Maximum Input Capacitance, Select Inputs Analog I/O Common I/O Feedthrough CIN CNO or CNC CCOM C(ON) 8 10 10 1.0 pF
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Symbol BW VCC V 3.0 4.5 6.0 3.0 3.0 4.5 6.0 3.0 3.0 4.5 6.0 3.0 5.0 3.0 VEE V 0.0 0.0 0.0 -3.0 0.0 0.0 0.0 -3.0 0.0 0.0 0.0 -3.0 0.0 -3.0 Typ 25C 80 90 95 95 -93 -93 -93 -93 -2 -2 -2 -2 9.0 12 Unit MHz
Parameter Maximum On-Channel Bandwidth or Minimum Frequency Response
Condition VIS = 1/2 (VCC - VEE) Source Amplitude = 0 dBm (Figures 10 and 22) f =100 kHz; VIS = 1/2 (VCC - VEE) Source = 0 dBm (Figures 12 and 22) VIS = 1/2 (VCC - VEE) Source = 0 dBm (Figures 10 and 22) VIN = VCC to VEE, fIS = 1 kHz, tr = tf = 3 ns RIS = 0 W, CL= 1000 pF, Q = CL * DVOUT (Figures 16 and 23) fIS = 1 MHz, RL = 10 KW, CL = 50 pF, VIS = 5.0 VPP sine wave VIS = 6.0 VPP sine wave (Figure 13)
Off-Channel Feedthrough Isolation
VISO
dB
Maximum Feedthrough On Loss
VONL
dB
Charge Injection
Q
pC
Total Harmonic Distortion THD + Noise
THD 6.0 3.0 0.0 -3.0 0.10 0.05
%
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NLAS4051
100 10 80 1 0.1 0.01 0.001 0.0001 0.00001 -40 VCC = 3.0 V 20 VCC = 5.0 V -20 0 20 60 80 100 120 0 -4.0 -2.0 0 2.0 VIS (VDC) 4.0 6.0 RON (W) ICC (nA) 60 2.0 V 100
40 3.0 V 4.5 V 5.5 V
Temperature (C)
Figure 3. ICC versus Temp, VCC = 3 V and 5 V
50
Figure 4. RON versus VCC, Temp = 255C
100 90 80 70 RON (W) 60 50 40 30 20 10 0 -55C 85C 25C RON (W) 125C
125C 40 25C 85C
30
20 -55C 10 0
0.5
1.0 VCom (V)
1.5
2.0
0
0.5
1.0
1.5 VCom (V)
2.0
2.5
3.0
Figure 5. Typical On Resistance VCC = 2.0 V, VEE = 0 V
25 85C 20 15 25C 10 -55C 5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 0 0.5 125C 20 85C 25
Figure 6. Typical On Resistance VCC = 3.0 V, VEE = 0 V
125C
RON (W)
RON (W)
15
10
25C
-55C
0 0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VCom (V)
VCom (V)
Figure 7. Typical On Resistance VCC = 4.5 V, VEE = 0 V
Figure 8. Typical On Resistance VCC = 5.5 V, VEE = 0 V
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NLAS4051
25 125C 20 85C
RON (W)
15
10
25C
-55C
5
0 -4
-2
0 VCom (V)
2
4
Figure 9. Typical On Resistance VCC = 3.3 V, VEE = -3.3 V
50 40 PHASE SHIFT 18%/DIV (dB) 30 BANDWIDTH (dB) 20 10 0 -10 -20 -30 -40 -50 0.1 1.0 10 100 FREQUENCY (mHz) BANDWIDTH (ON-RESPONSE)
90 72 54 36 18 0 -18 -36 -54 -72 -90 0.1 1.0 10 100 FREQUENCY (mHz) PHASE SHIFT
Figure 10. Bandwidth, VCC = 5.0 V
Figure 11. Phase Shift, VCC = 5.0 V
0 -10 OFF ISOLATION 10 dB/DIV -20 -30 -40 -50 -60 -70 -80 -90 -100 0.1 1.0 10 100 FREQUENCY (mHz) DISTORTION (%)
0
3.0 5.5 0.1 $3.3 4.5
0.01 10 100 1000 10000 10000 FREQUENCY (mHz)
Figure 12. Off Isolation, VCC = 5.0 V
Figure 13. Total Harmonic Distortion
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NLAS4051
30 TA = 25_C 25 20 15 10 5 0 2.5 tOFF (ns) tON (ns) TIME (ns) 25 20 15 10 5 0 -55 tON tOFF 30 VCC = 4.5 V
TIME (ns)
3
3.5
4
4.5
5
-40
25 Temperature (C)
85
125
VCC (VOLTS)
Figure 14. tON and tOFF versus VCC
Figure 15. tON and tOFF versus Temp
3.0 2.5
100
10
2.0 Q (pC) 1.5 1.0 0.5 0 -0.5 0 1
LEAKAGE (nA)
VCC = 5 V
1
ICOM(ON)
0.1
VCC = 3 V
0.01
ICOM(OFF) VCC = 5.0 V INO(OFF)
0.001
2 VCOM (V)
3
4
5
-55
-20
25
70
85
125
TEMPERATURE (C)
Figure 16. Charge Injection versus COM Voltage
Figure 17. Switch Leakage versus Temperature
VCC 0.1 mF VEE
Output VOUT 300 W 35 pF
VCC Input 0V VCC Output 50% 50%
90%
Address Select Pin VEE 10%
ttrans
ttrans
Figure 18. Channel Selection Propagation Delay
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NLAS4051
DUT VCC 0.1 mF 300 W Output VOUT 35 pF Output Input GND tBMM 90% 90% of VOH VCC
Address Select Pin
GND
Figure 19. tBBM (Time Break-Before-Make)
VCC DUT VCC 0.1 mF Open Output VOUT 300 W 35 pF Output GND tON tOFF Input 0V VOH 90% 90% 50% 50%
Input
Enable
Figure 20. tON/tOFF
VCC DUT Output Open 300 W VOUT 35 pF Input
VCC 50% 0V VCC Output VOL tOFF 10% tON 10% 50%
Input
Enable
Figure 21. tON/tOFF
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NLAS4051
50 W Reference Input Output 50 W Generator 50 W DUT Transmitted
Channel switch Address and Inhibit/s test socket is normalized. Off isolation is measured across an off channel. On loss is the bandwidth of an On switch. VISO, Bandwidth and VONL are independent of the input signal direction. VISO = Off Channel Isolation = 20 Log VONL = On Channel Loss = 20 Log VOUT VIN for VIN at 100 kHz
VOUT VIN
for VIN at 100 kHz to 50 MHz
Bandwidth (BW) = the frequency 3 dB below VONL
Figure 22. Off Channel Isolation/On Channel Loss (BW)/Crosstalk (On Channel to Off Channel)/VONL
DUT Open Output VIN
VCC GND CL Output Off Off DVOUT
VIN
On
Figure 23. Charge Injection: (Q)
TYPICAL OPERATION
+5.0 V 16 VCC 16 +3.0 V VCC
7 GND 8
VEE
VEE GND -3.0 V
7 8
Figure 24. 5.0 Volts Single Supply VCC = 5.0 V, VEE = 0
Figure 25. Dual Supply VCC = 3.0 V, VEE = -3.0 V
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NLAS4051
PACKAGE DIMENSIONS
SOIC-16 D SUFFIX CASE 751B-05 ISSUE J
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
TSSOP-16 CASE 948F-01 ISSUE A
16X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16
2X
L/2
9
J1 B -U-
L
PIN 1 IDENT. 1 8
J
N 0.15 (0.006) T U
S
0.25 (0.010) M
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
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EEE CCC EEE CCC
SECTION N-N
-W-
DIM A B C D F G H J J1 K K1 L M
NLAS4051
PACKAGE DIMENSIONS
QSOP-16 QS SUFFIX CASE 492-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. THE BOTTOM PACKAGE SHALL BE BIGGER THAN THE TOP PACKAGE BY 4 MILS (NOTE: LEAD SIDE ONLY). BOTTOM PACKAGE DIMENSION SHALL FOLLOW THE DIMENSION STATED IN THIS DRAWING. 4. PLASTIC DIMENSIONS DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 6 MILS PER SIDE. 5. BOTTOM EJECTOR PIN WILL INCLUDE THE COUNTRY OF ORIGIN (COO) AND MOLD CAVITY I.D. MOLD PIN MARK INCHES DIM MIN MAX A 0.189 0.196 B 0.150 0.157 C 0.061 0.068 D 0.008 0.012 F 0.016 0.035 G 0.025 BSC H 0.008 0.018 J 0.0098 0.0075 K 0.004 0.010 L 0.230 0.244 M 0_ 8_ N 0_ 7_ P 0.007 0.011 Q 0.020 DIA R 0.025 0.035 U 0.025 0.035 V 0_ 8_ MILLIMETERS MIN MAX 4.80 4.98 3.81 3.99 1.55 1.73 0.20 0.31 0.41 0.89 0.64 BSC 0.20 0.46 0.249 0.191 0.10 0.25 5.84 6.20 0_ 8_ 0_ 7_ 0.18 0.28 0.51 DIA 0.64 0.89 0.64 0.89 0_ 8_
-A- R
Q
H x 45_ U
RAD. 0.013 X 0.005 DP. MAX
-B-
RAD. 0.005-0.010 TYP
L 0.25 (0.010)
M
G T P DETAIL E
C
K
V N 8 PL -T-
D 16 PL 0.25 (0.010)
M
SEATING PLANE
TB
S
A
S
J M
F DETAIL E
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NLAS4051/D

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Price & Availability of NLAS4051

	To Download NLAS4051 Datasheet File
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